The present invention relates to an arithmetic circuit, an adaptive filter and an echo canceler, each formed as a semiconductor integrated circuit, and more specifically to a technique effectively applied for reducing the power consumption of, for example, an echo canceling LSI for ISDN (Integrated Services Digital Network).
Adaptive filters such as transversal filters are the ones that can change their characteristics in response to changes over time in the input signal. That is, this kind of filter performs two calculations: an output calculation whereby the input signal is multiplied by tap coefficients and the multiplied values are summed up for a predetermined number of taps to produce a filter output; and an update calculation consisting of multiplication and addition whereby the tap coefficients are updated according to an error signal which is the difference between the filter output and a signal from a certain object system to which the filter output is made to respond. According to the result of the update calculation, the filter rewrites the tap coefficients in chronological order so as to change the filter characteristics in real time. Where such an adaptive filter is formed by a digital signal processor, the updating of the tap coefficients can be realized by an integral processing which involves adding an update amount to a tap coefficient read out from memory and writing the updated tap coefficient into the same address.
The digital signal processor has in addition to the arithmetic and logic unit a multiplier as hardware, which makes multiplication and addition more efficient, improving the real time digital signal processing capability. As an example of this kind of digital signal processor may be united a DSP "TMS320C25," introduced in user's manual for second-generation digital signal processor TMS320C25, p. 3-2-p. 3-6, 1989 published by Texas Instruments Japan, Ltd.